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June 2005 rev 1.0 Low Voltage 1:18 Clock Distribution Chip
Features
ASM2I9940L
With low output impedance (20), in both the HIGH and LVPECL or LVCMOS Clock Input 2.5V LVCMOS Outputs for Pentium II Microprocessor Support* 150pS Maximum Output-to-Output Skew Maximum Output Frequency of 250MHz 32 Lead LQFP & TQFP Packaging Dual or Single Supply Device: Dual VCC Supply Voltage, 3.3V Core and 2.5V Output Single 3.3V VCC Supply Voltage for 3.3V Outputs Single 2.5V VCC Supply Voltage for 2.5V I/O Pin and Function compatible to MPC940L, MPC9109, CY29940 and CY29940-1 LOW logic states, the output buffers of the ASM2I9940L are ideal for driving series terminated transmission lines. With a 20 output impedance the ASM2I9940L has the capability of driving two series terminated lines from each output. This gives the device an effective fanout of 1:36. The differential LVPECL inputs of the ASM2I9940L allow the device to interface directly with a LVPECL fanout buffer to build very wide clock fanout trees or to couple to a high frequency clock source. The LVCMOS input provides a more standard interface for applications requiring only a single clock distribution chip at relatively low frequencies. In addition, the two clock sources can be used to provide for a test clock interface as well as the primary system clock. A logic HIGH on the LVCMOS_CLK_Sel pin will select the LVCMOS level clock input. All inputs of the ASM2I9940L have internal pullup/pulldown resistor, so they can be left open if unused. The ASM2I9940L is a single or dual supply device. The device power supply offers a high degree of flexibility. The device can operate with a 3.3V core and 3.3V output, a 3.3V core and 2.5V outputs as well as a 2.5V core and 2.5V outputs. The 32-lead LQFP and TQFP Packages were chosen to optimize performance, board space and cost of the device. The 32-lead LQFP and TQFP Packages have a 7x7mm2 body size with conservative 0.8mm pin spacing.
Functional Description
The ASM2I9940L is a 1:18 low Voltage Clock distribution chip with 2.5V or 3.3V LVCMOS output capabilities. The device features the capability to select either a differential LVPECL or LVCMOS compatible input. The 18 outputs are 2.5V or 3.3V LVCMOS compatible and feature the drive strength to drive 50 series or parallel terminated transmission lines. With output-to-output skews of 150pS, the ASM2I9940L is ideal as a clock distribution chip for the most demanding of Synchronous systems. The 2.5V outputs also make the device ideal for supplying clocks for a high performance microprocessor based design.
* Pentium II is a trademark of Intel Corporation
Alliance Semiconductor 2575, Augustine Drive * Santa Clara, CA * Tel: 408.855.4900 * Fax: 408.855.4999 * www.alsc.com
Notice: The information in this document is subject to change without notice.
June 2005 rev 1.0
Block Diagram
PECL_CLK PECL_CLK 0
ASM2I9940L
Q0 LVCMOS_CLK LVCMOS_CLK_Sel (Internal Pulldown) Q17 1 16 Q1-Q16
Pin Diagram
GNDO 17 16 15 14 VCCO Q12 Q13 Q14 GNDO Q15 Q16 Q17 13 12 11 10 9 1 2 3 4 5 6 7 8 VCCO
Q10 19 PECL_CLK
24 GNDO Q5 Q4 Q3 VCC0 Q2 Q1 Q0 25 26 27 28 29 30 31 32
23
22
21
20
ASM2I9940L
LVCMOS_CLK_Sel
GNDO
LVCMOS_CLK
PECL_CLK
GNDI
Table 1. Function Table LVCMOS_CLK_Sel
0 1
Table 2. Power Supply Voltages Input
PECL_CLK LVCMOS_CLK
Supply Pin
VCCI VCCO
VCCI
Q11 18
VCCI
Q6
Q7
Q8
Q9
Voltage Level
2.5V or 3.3V 5% 2.5V or 3.3V 5%
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Table 3. Pin Configurations Pin #
5 6 3 4 32,31,30,28,27,26,24,23,22, 20,19,18,15,14,13,11,10,9 2 1,12,17,25 7,21 8, 16,29
ASM2I9940L
Pin Name
PECL_CLK PECL_CLK LVCMOS_CLK LVCMOS_CLK_Sel Q0-Q17 GNDI GNDO VCCI VCCO
I/O
Input Input Input Output
Type
LVPECL LVCMOS LVCMOS LVCMOS Supply Supply Supply Supply
Function
LVPECL Clock Inputs LVCMOS Clock Input Selects either LVPECL or LVCMOS input as Clock Source Clock Outputs Core Negative Power Supply Output Negative Power Supply Core Positive Power Supply Output Positive Power Supply
Table 4. Absolute Maximum Ratings1 Symbol
VCC VI IIN TStor Ts TDV Supply Voltage Input Voltage Input Current Storage Temperature Range Max. Soldering Temperature (10 sec) Static Discharge Voltage (As per JEDEC STD22- A114-B)
Parameter
Min
-0.3 -0.3 -40
Max
3.6 VCC + 0.3 20 125 260 2
Unit
V V mA C C KV
Note:1. These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect device reliability.
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Table 5. DC Characteristics (TA = 0 to 70C, VCCI = 3.3V 5%, VCCO = 3.3V 5% Symbol
VIH VIL VPP VCMR VOH VOL IIN CIN Cpd ZOUT ICC
)
ASM2I9940L
Characteristic
Input HIGH Voltage Input LOW Voltage Peak-to-Peak Input Voltage Common Mode Range Output HIGH Voltage Output LOW Voltage Input Current Input Capacitance Power Dissipation Capacitance Output Impedance Maximum Quiescent Supply Current CMOS_CLK CMOS_CLK PECL_CLK PECL_CLK
Min
2.4 500 VCC-1.4 2.4
Typ
Max
VCCI 0.8 1000 VCC-0.6 0.5 200
Unit
V V mV V V V A pF pF
Condition
IOH = -20mA IOH = 20mA
4.0 10 18 23 0.5 28 1.0
per output
mA
Table 6. AC Characteristics (TA = 0 to 70C, VCCI = 3.3V 5%, VCCO = 3.3V 5%) Symbol
Fmax tPLH tPLH tsk(o) tsk(pp) tsk(pp) tsk(pp) DC tr, tf Part-to-Part Skew Part-to-Part Skew Part-to-Part Skew Output Duty Cycle Output Rise/Fall Time
Characteristic
Maximum Input Frequency Propagation Delay Propagation Delay Output-to-output Skew PECL_CLK < 150MHz CMOS_CLK < 150MHz PECL_CLK > 150MHz CMOS_CLK > 150MHz PECL_CLK CMOS_CLK PECL_CLK < 150MHz CMOS_CLK < 150MHz PECL_CLK > 150MHz CMOS_CLK > 150MHz PECL_CLK CMOS_CLK fCLK < 134 MHz fCLK <250 MHz
Min
2.0 1.7 2.0 1.8
Typ
2.7 2.5 2.9 2.5
Max
250 3.4 3.0 3.7 3.2 150 150 1.5 1.3 1.8 1.5 850 750 55 60 1.1
Unit
MHz nS nS pS nS nS pS % % nS
Condition
Note1.
Note1. Notes1,2 Notes1,2 Notes
1,3
45 40 0.3
50 50
Input DC = 50% Input DC = 50% 0.5 - 2.4 V
Note: 1. Tested using standard input levels, Production tested @ 150MHz. 2. Across temperature and voltage ranges, includes output skew. 3. For a specific temperature and voltage, includes output skew.
Low Voltage 1:18 Clock Distribution Chip
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Table 7. DC Characteristics (TA = 0 to 70C, VCCI = 3.3V 5%, VCCO = 2.5V 5%) Symbol
VIH VIL VPP VCMR VOH VOL IIN CIN Cpd ZOUT ICC
ASM2I9940L
Characteristic
Input HIGH Voltage Input LOW Voltage Peak-to-Peak Input Voltage Common Mode Range Output HIGH Voltage Output LOW Voltage Input Current Input Capacitance Power Dissipation Capacitance Output Impedance Maximum Quiescent Supply Current CMOS_CLK CMOS_CLK PECL_CLK PECL_CLK
Min
2.4 500 VCC-1.4 1.8
Typ
Max
VCCI 0.8 1000 VCC-0.6 0.5 200
Unit
V V mV V V V A pF pF
Condition
IOH = -20mA IOH = 20mA
4.0 10 23 0.5 1.0
per output
mA
Table 8. AC Characteristics (TA = 0 to 70C, VCCI = 3.3V 5%, VCCO = 2.5V 5% ) Symbol
Fmax tPLH tPLH tsk(o) tsk(pp) tsk(pp) tsk(pp) DC tr, tf Part-to-Part Skew Part-to-Part Skew Part-to-Part Skew Output Duty Cycle Output Rise/Fall Time
Characteristic
Maximum Input Frequency Propagation Delay Propagation Delay Output-to-output Skew PECL_CLK < 150MHz CMOS_CLK < 150MHz PECL_CLK > 150MHz CMOS_CLK > 150MHz PECL_CLK CMOS_CLK PECL_CLK < 150MHz CMOS_CLK < 150MHz PECL_CLK > 150MHz CMOS_CLK > 150MHz PECL_CLK CMOS_CLK fCLK < 134 MHz fCLK <250 MHz
Min
2.0 1.7 2.0 1.8
Typ
2.8 2.5 2.9 2.5
Max
250 3.5 3.0 3.8 3.3 150 150 1.5 1.3 1.8 1.5 850 750 55 60 1.2
Unit
MHz nS nS pS nS nS pS % % nS
Condition
Note1.
Note1 Notes1,2 Notes1,2 Notes
1,3
45 40 0.3
50 50
Input DC = 50% Input DC = 50% 0.5 - 1.8 V
Note: 1.Tested using standard input levels, Production tested @ 150MHz. 2. Across temperature and voltage ranges, includes output skew. 3. For a specific temperature and voltage, includes output skew.
Low Voltage 1:18 Clock Distribution Chip
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Table 9. DC Characteristics (TA = 0 to 70C, VCCI = 2.5V 5%, VCCO = 2.5V 5%) Symbol
VIH VIL VPP VCMR VOH VOL IIN CIN Cpd ZOUT ICC
ASM2I9940L
Characteristic
Input HIGH Voltage Input LOW Voltage Peak-to-Peak Input Voltage Common Mode Range Output HIGH Voltage Output LOW Voltage Input Current Input Capacitance Power Dissipation Capacitance Output Impedance Maximum Quiescent Supply Current CMOS_CLK CMOS_CLK PECL_CLK PECL_CLK
Min
2.4 500 VCC-1.0 1.8
Typ
Max
VCCI 0.8 1000 VCC-0.6 0.5 200
Unit
V V mV V V V A pF pF
Condition
IOH = -20mA IOH = 20mA
4.0 10 18 23 0.5 28 1.0
per output
mA
Table 10. AC Characteristics (TA = 0 to 70C, VCCI = 2.5V 5%, VCCO = 2.5V 5%) Symbol
Fmax tPLH tPLH tsk(o) tsk(pp) tsk(pp) tsk(pp) DC tr, tf Propagation Delay Propagation Delay Output-to-output Skew Within one bank Part-to-Part Skew Part-to-Part Skew Part-to-Part Skew Output Duty Cycle Output Rise/Fall Time
Characteristic
Maximum Input Frequency PECL_CLK < 150MHz CMOS_CLK < 150MHz PECL_CLK > 150MHz CMOS_CLK > 150MHz PECL_CLK CMOS_CLK PECL_CLK < 150MHz CMOS_CLK < 150MHz PECL_CLK > 150MHz CMOS_CLK > 150MHz PECL_CLK CMOS_CLK fCLK < 134 MHz fCLK <250 MHz
Min
2.6 2.3 2.8 2.3
Typ
4.0 3.1 3.8 3.1
Max
200 5.2 4.0 5.0 4.0 200 200 2.6 1.7 2.2 1.7 1.2 1.0 55 60 1.2
Unit
MHz nS nS pS nS nS nS % % nS
Condition
Note1.
Note1. Notes1,2 Notes1,2 Notes1,3 Input DC = 50% Input DC = 50% 0.5 - 1.8 V
45 40 0.3
50 50
Note: 1. Tested using standard input levels, Production tested @ 150MHz. 2. Across temperature and voltage ranges, includes output skew. 3. For a specific temperature and voltage, includes output skew.
Low Voltage 1:18 Clock Distribution Chip
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Pulse Generator Z=50 Z0=50 ASM2I9940L Z0=50
ASM2I9940L
RT=50
RT=50
VTT
VTT
Figure 1. LVCMOS_CLK ASM2I9940L AC Test Reference for VCC = 3.3V and VCC = 2.5V
Differential Pulse Generator Z=50 Z0=50 ASM2I9940L Z0=50
RT = 50 RT=50 VTT VTT
Figure 2. PECL_CLK ASM2I9940L AC Test Reference for VCC = 3.3V and VCC = 2.5V
PECL_CLK PECL_CLK VPP VCMR LVCMOS_CLK VC VCC /2 GND VCC VCC /2 Q tPD GND Q tPD VC VCC /2 GND
Figure 3. Propagation Delay (tPD) Test Reference
VCC VCC /2 GND tP
Figure 4. LVCMOS Propagation Delay (tPD) Test Reference
VCC VCC /2 GND VOH
T0 DC (tP /T0 100%) tSK(O)
VCC /2 GND
The time from the PLL controlled edge to the non-controlled edge, divided by the time between PLL controlled edges, expressed as a percentage.
The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device
Figure 5. Output Duty Cycle (DC)
VCC = 3.3V VCC = 2.5V 2.4 0.55 tF tR 1.8V 0.6V tF
Figure 6. Output-to-Output Skew tSK(O)
VCC = 3.3V VCC = 2.5V 2.0 0.8 tR 1.7V 0.7V
Figure 7. Output Transition Time Test Reference
Figure 8. Input Transition Time Test Reference
Low Voltage 1:18 Clock Distribution Chip
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Power Consumption of the ASM2I9940L and Thermal Management
The ASM2I9940L AC specification is guaranteed for the entire operating frequency range up to 250MHz. The ASM2I9940L power consumption and the associated long-term reliability may decrease the maximum frequency limit, depending on operating conditions such as clock frequency, supply voltage, output loading, ambient temperature, vertical convection and thermal conductivity of package and board. This section describes the impact of these parameters on the junction temperature and gives a guideline to estimate the ASM2I9940L die junction temperature and the associated device reliability.
ASM2I9940L
Where ICCQ is the static current consumption of the ASM2I9940L, CPD is the power dissipation capacitance per output, (M)CL represents the external capacitive output load, N is the number of active outputs (N is always 12 in case of the ASM2I9940L). The ASM2I9940L supports driving transmission lines to maintain high signal integrity and tight timing parameters. Any transmission line will hide the lumped capacitive load at the end of the board trace, therefore, CL is zero for controlled transmission line systems and can be eliminated from equation 1. Using parallel termination output termination results in equation 2 for power dissipation. In equation 2, P stands for the number of outputs with a parallel or thevenin termination, VOL, IOL, VOH and IOH are a function of the output termination technique and DCQ is the clock signal duty cycle. If transmission lines are used CL is zero in equation 2 and can be eliminated. In general, the use of controlled transmission line techniques eliminates the impact of the lumped capacitive loads at the end lines and greatly reduces the power dissipation of the device. Equation 3 describes the die junction temperature TJ as a function of the power consumption. Where Rthja is the thermal impedance of the package (junction to ambient) and TA is the ambient temperature. According to Table 11, the junction temperature can be used to estimate the long-term device reliability. Further, combining equation 1 and equation 2 results in a maximum operating frequency for the ASM2I9940L in a series terminated transmission line system, equation 4.
Table 11. Die junction temperature and MTBF Junction temperature (C)
100 110
MTBF (Years)
20.4 9.1
120 4.2 130 2.0 Increased power consumption will increase the die junction temperature and impact the device reliability (MTBF). According to the system-defined tolerable MTBF, the die junction temperature of the ASM2I9940L needs to be controlled and the thermal impedance of the board/package should be optimized. The power dissipated in the ASM2I9940L is represented in equation 1.
PTOT = I CCQ + VCC f CLOCK N C PD + C L VCC M PTOT = VCC I CCQ + VCC f CLOCK N C PD + C L + DC Q I OH (VCC - VOH ) + (1 - DC Q ) I OL VOL M P T J = T A + PTOT Rthja
Equation 1
[
]
Equation 2 Equation 3 Equation 4
f CLOCKMAX =
C PD
1 2 N VCC
T - TA JMAX - (I CCQ VCC ) Rthja
Low Voltage 1:18 Clock Distribution Chip
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TJ,MAX should be selected according to the MTBF system requirements and Table 11. Rthja can be derived from Table 12. The Rthja represent data based on 1S2P boards, using 2S2P boards will result in a lower thermal impedance than indicated below.
ASM2I9940L
If the calculated maximum frequency is below 250MHz, it becomes the upper clock speed limit for the given application conditions. The following eight derating charts describe the safe frequency operation range for the ASM2I9940L. The charts were calculated for a maximum tolerable die junction temperature of 110C (120C), corresponding to an estimated MTBF of 9.1 years (4 years), a supply voltage of 3.3V and series terminated transmission line or capacitive loading. Depending on a given set of these operating conditions and the available device convection a decision on the maximum operating frequency can be made.
Table 12. Thermal package impedance of the 32LQFP Convection, Rthja (1P2S Rthja (2P2S board), C/W board), C/W LFPM
Still air 100 lfpm 200 lfpm 300 lfpm 400 lfpm 500 lfpm 86 76 71 68 66 60 61 56 54 53 52 49
Low Voltage 1:18 Clock Distribution Chip
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Package Information 32-lead TQFP Package
ASM2I9940L
SECTION A-A
Dimensions Symbol
A A1 A2 D D1 E E1 L L1 T T1 b b1 R0 a e
Inches Min Max
.... 0.0020 0.0374 0.3465 0.2717 0.3465 0.2717 0.0177 0.0035 0.0038 0.0118 0.0118 0.0031 0 0.0472 0.0059 0.0413 0.3622 0.2795 0.3622 0.2795 0.0295 0.0079 0.0062 0.0177 0.0157 0.0079 7
Millimeters Min Max
... 0.05 0.95 8.8 6.9 8.8 6.9 0.45 0.09 0.097 0.30 0.30 0.08 0 1.2 0.15 1.05 9.2 7.1 9.2 7.1 0.75 0.2 0.157 0.45 0.40 0.2 7
0.03937 REF
1.00 REF
0.031 BASE
0.8 BASE
Low Voltage 1:18 Clock Distribution Chip
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32-lead LQFP Package
ASM2I9940L
SECTION A-A
Dimensions Symbol
A A1 A2 D D1 E E1 L L1 T T1 b b1 R0 e a
Inches Min Max
.... 0.0020 0.0531 0.3465 0.2717 0.3465 0.2717 0.0177 0.0035 0.0038 0.0118 0.0118 0.0031 0 0.0630 0.0059 0.0571 0.3622 0.2795 0.3622 0.2795 0.0295 0.0079 0.0062 0.0177 0.0157 0.0079 7
Millimeters Min Max
... 0.05 1.35 8.8 6.9 8.8 6.9 0.45 0.09 0.097 0.30 0.30 0.08 0 1.6 0.15 1.45 9.2 7.1 9.2 7.1 0.75 0.2 0.157 0.45 0.40 0.20 7
0.03937 REF
1.00 REF
0.031 BASE
0.8 BASE
Low Voltage 1:18 Clock Distribution Chip
Notice: The information in this document is subject to change without notice.
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Ordering Information Part Number
ASM2I9940L-32-LT ASM2I9940L-32-LR ASM2I9940LG-32-LT ASM2I9940LG-32-LR ASM2I9940L-32-ET ASM2I9940L-32-ER ASM2I9940LG-32-ET ASM2I9940LG-32-ER
ASM2I9940L
Marking
ASM2I9940LL ASM2I9940LL ASM2I9940LGL ASM2I9940LGL ASM2I9940LE ASM2I9940LE ASM2I9940LGE ASM2I9940LGE
Package Type
32-pin LQFP, Tray 32-pin LQFP, Tape and Reel 32-pin LQFP, Tray, Green 32-pin LQFP, Tape and Reel, Green 32-pin TQFP, Tray 32-pin TQFP ,Tape and Reel 32-pin TQFP, Tray, Green 32-pin TQFP ,Tape and Reel, Green
Operating Range
Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial
Device Ordering Information
ASM2I9940LG-32-LR
R = Tape & reel, T = Tube or Tray O = SOT S = SOIC T = TSSOP A = SSOP V = TVSOP B = BGA Q = QFN DEVICE PIN COUNT F = LEAD FREE AND RoHS COMPLIANT PART G = GREEN PACKAGE PART NUMBER X= Automotive I= Industrial P or n/c = Commercial (-40C to +125C) (-40C to +85C) (0C to +70C) 1 = Reserved 2 = Non PLL based 3 = EMI Reduction 4 = DDR support products 5 = STD Zero Delay Buffer 6 = Power Management 7 = Power Management 8 = Power Management 9 = Hi Performance 0 = Reserved U = MSOP E = TQFP L = LQFP U = MSOP P = PDIP D = QSOP X = SC-70
ALLIANCE SEMICONDUCTOR MIXED SIGNAL PRODUCT
Licensed under US patent #5,488,627, #6,646,463 and #5,631,920.
Low Voltage 1:18 Clock Distribution Chip
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ASM2I9940L
Alliance Semiconductor Corporation 2575, Augustine Drive, Santa Clara, CA 95054 Tel# 408-855-4900 Fax: 408-855-4999 www.alsc.com
Copyright (c) Alliance Semiconductor All Rights Reserved Part Number: ASM2I9940L Document Version: 1.0
Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to Alliance Semiconductor, dated 11-11-2003
(c) Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.
Low Voltage 1:18 Clock Distribution Chip
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